1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM), more particularly relates to such a device that multiple memory cells are stacked on a semiconductor substrate to constitute a NAND cell unit, and a method of fabricating the same.
2. Description of the Related Art
A NAND-type flash memory is known as one of EEPROMs. In the NAND-type flash memory, multiple memory cells are connected in series in such a manner that adjacent two cells share a source/drain diffusion layer, thereby constituting a NAND cell unit. By use of this cell array arrangement, the unit cell area is smaller that that of a NOR-type one, and it is easy to increase the capacitance.
Further, since the NAND-type flash memory uses tunneling current for writing data, the consumption current is smaller than that of the NOR-type one, which uses hot-carrier injection. Therefore, it is possible to make a page capacitance defined as a simultaneously written cell range large, whereby it becomes possible to perform high-speed write/read.
To make the storage density of a unit area higher with the conventional structure, in which memory cells are formed in a single layer, it is in need of progressing the miniaturization or using a multi-level storage scheme. However, there is a limit for miniaturization. The increase of memory density based on the multi-level storage scheme also has a limit defined by data reliability.
By contrast, to make a NAND-type flash memory highly integrated, there has already been provided such a scheme as to stack memory cells on the semiconductor substrate (for example, refer to Patent Document 1: Unexamined Japanese Patent Application Publication No. 2005-85938). However, there are some problems in the disclosed method in this document as follows.
First, the channel regions and source/drain regions of memory cells in the NAND cell unit are formed to have different conductivity types from each other like that in the conventional, planar type NAND cell unit. Therefore, as the NAND cell unit is more miniaturized, the short-channel effect will become larger.
Second, in case the number of stacked memory cells is increased, i.e., the height of the memory cell unit (unit length) is enlarged, the aspect ratio also is increased. It will not only injure the process reliability but also cause the memory cell's operation delay.
Third, to achieve such a structure that a floating gate and a control gate are stacked in perpendicular to the side wall of a semiconductor pillar, it is necessary to repeatedly bury a highly resistive dielectric film for every memory cell formation process. Therefore, the number of processes is increased in proportion to the number of memory cells, and it leads to reliability reduction.
Another NAND-type flash memory, which has a possibility of solving the above described problems, has already been provided prior to the above-described Patent Application (refer to Patent Document 2: Unexamined Japanese Patent Application Publication No. 10-93083). In this Document 2, there is disclosed a NAND-type flash memory with vertical memory cells stacked, in which a gate wiring stack structure is previously formed, and semiconductor activation layers are formed opposite to the sidewalls of the gate wirings, respectively, with gate insulating films interposed therebetween.
However, in the Patent Document 2, after having patterned the gate wiring stack body and prior to the silicon layer formation, the source diffusion layer of NAND cell units (NAND strings) is formed by a selective diffusion method. This is because of that in case of p-type of channel bodies, and n-channel type of NAND cell units, it is in need of making the p-type silicon layer contacted with the p-type substrate. However, according to this method, the select gate transistor formed at the lowest portion of the silicon layer becomes to have an offset gate structure, in which the source diffusion layer is formed as separated from the gate edge. There is not provided a measure for avoiding such the problem. If as it is, it is impossible to achieve a desired operation of a NAND-type flash memory
Further, in the Patent Document 2, a polycrystalline silicon film is used as word lines and select gate lines. Therefore, there is a limit for making the resistance of the word lines and select gate lines low, and it is difficult to achieve a usual NAND-type flash memory.